View TA1318AFG_4114762.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TA1318AFG
TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic
TA1318AFG
SYNC Processor, Frequency Counter IC for TV Component Signals
TA1318AFG is a sync processor for TV component signals. TA1318AFG provides sync and frequency counter processing for external input signals. These functions are integrated in a 30 pin SSOP-type plastic package. TA1318AFG provides I2C bus interface, so various functions and controls are adjustable via the bus.
Features
* * * * * * * * * * Horizontal synchronization circuit (15.75 kHz, 31.5 kHz, 33.75 kHz, 45 kHz) Horizontal and vertical frequency counter Horizontal PLL Accepts 2-level and 3-level sync Accepts both negative and positive HD and VD Clamp pulse output HD, VD output (polarity inverter) Separated sync output Mask for the copy guard signal Weight: 0.63 g (typ.)
Vertical synchronization circuit (525I, 525P, 625I, 750P, 1125I, 1125P, PAL 100 Hz, NTSC 120 Hz)
1
2006-02-27
TA1318AFG
Block Diagram
DAC3 30 DAC3 SW VD2-OUT 29 INV SW VD1-OUT 28 INV SW NC 27 SYNC1-IN 26 SYNC SEPA DAC1 25 DAC1 SW SYNC2-IN Address SW 24 SYNC SEPA 23 SCL 22 I CBUS Decoder
2
SDA 21
NC 20
HD2-OUT Digital GND 19 INV SW 18
NC 17
HD1-OUT 16 INV SW
TEST DAC3
DV2-OUT SW
DV1-OUT SW
DAC1
HD2-OUT SW
HD1-OUT SW
V-Input SW H/VFREQ Counter V-FREQ DET SW Clamp Pulse
V C/D
V-FREQ SW
V-SYNC
DAC2
CP SW
H/CSYNC
DAC2 SW
V Integral
HD Polarity
2 x fH
H-FREQ DET SW
H-INPUT SW
H-AFC
H C/D
H-Ramp
HVCO
H-FREQ SW
1 HD2-IN
2 VD2-IN
3 HD1-IN
4 VD1-IN
5 Analog GND
6 NC
7 AFC Filter
8 NC
9 HVCO
10 NC
11 VCC
12 DAC2
13 VD3-IN
14 HD3-IN
15 CP-OUT
2
2006-02-27
TA1318AFG
Pin Functions
Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal
11 Input horizontal sync signal. 1 HD2-IN It accepts input of both positive and negative polarity. Input signal from this pin is not synchronized. 1 1 k 50 k
Th: 0.7 V
or
Th: 0.7 V 5
11 Th: 0.7 V Input vertical sync signal. 2 VD2-IN It accepts input of both positive and negative polarity. Input signal from this pin is not synchronized. 2 1 k 45 k or
Th: 0.7 V 5
3
2006-02-27
TA1318AFG
Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal
11 Input horizontal sync signal. 3 HD1-IN It accepts input of both positive and negative polarity. Input signal from this pin is not synchronized. 3 1 k 50 k
Th: 0.7 V
or
Th: 0.7 V 5
11 Th: 0.7 V Input vertical sync signal. 4 VD1-IN It accepts input of both positive and negative polarity. Input signal from this pin is not synchronized. 4 1 k 45 k or
Th: 0.7 V 5
5 6
Analog GND N.C.
GND pin for analog circuit blocks. Connect to GND.

4
2006-02-27
TA1318AFG
Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal
11
Connect filter for horizontal AFC. 7 AFC Filter Voltage on this pin determines horizontal output frequency. 7 300 30 k DC
5
8
N.C.
Connect to GND.
11
Connect ceramic oscillator for horizontal oscillation. 9 HVCO 9 2 k Use Murata CSBLA503KECZF30.
4 k 1 k
1 k 10 k 5
10 11
N.C. VCC
Connect to GND. VCC pin. Connect 9 V (typ.).

5
2006-02-27
TA1318AFG
Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal
DAC2 output pin. 500 In Test mode, it outputs HD or composite sync signal to frequency counter. 12 DAC2 (H/C. SYNC output) To improve the driving ability, it is possible to connect a resister (minimum: 2 k) between this pin and GND. However, when the resister is added, the output DC voltage is down. 200 30 k
11
DC or H/C SYNC
7V 0V 18
12
11 Th: 0.7 V
Input vertical sync signal. 13 VD3-IN It accepts input of both positive and negative polarity. 13 1 k 45 k or
Th: 0.7 V 5
11
Th: 0.7 V
Input horizontal sync signal. 14 HD3-IN It accepts input of both positive and negative polarity. 14 1 k 50 k or
Th: 0.7 V 5
6
2006-02-27
TA1318AFG
Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal
11 500
5.0 V Clamp pulse (CP) output pin. 15 CP-OUT It outputs CP generated by sync circuit. 200 2.5 k 0V
15
18
11 HD output pin. Open collector output. 16 HD1-OUT HD1/HD2 input signals are output from this pin without synchronization. Polarity is switched by BUS write function. 18 16 200 or
17 18
N.C. Digital GND
Connect to GND. GND pin for logic blocks.

7
2006-02-27
TA1318AFG
Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal
11 HD output pin. Open collector output. 19 HD2-OUT HD1/HD2 input signals are output from this pin without synchronization. Polarity is switched by BUS write function. 18 19 200 or
20
N.C.
Connect to GND.
11
ACK
4 VF
21
SDA
SDA pin for I C bus.
2
50 21
20 k
SDA
5 18
8
2006-02-27
TA1318AFG
Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal
11
22
SCL
SCL pin for I C bus.
2
20 k 22
SCL 4 VF
5
15 k
11 9V DC/DD 7.5 V
100 k
Slave address switch pin. 23 Address SW When this pin is connected to VCC (GND), used for DC/DDH (D8/D9H); when left open, DA/DBH. 23
7.5 V 60 k DA/DB 1.5 V 100 k 15 k
1 k
100 k
1.5 V D8/D9 0V 5
9
2006-02-27
TA1318AFG
Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal White 100 = 1 Vp-p 11 1 k 1 k 1 k 24 SYNC2-IN Input Y signal (Note 1) for sync separation circuit. Input via clamp capacitor. 24 or 1 k 4 VF
5
DAC1 output pin. In Test mode, it outputs VD or composite sync signal to frequency counter. 25 DAC1 (V SYNC output) To improve the driving ability, it is possible to connect a resister (minimum: 2 k) between this pin and GND. However, when the resister is added, the output DC voltage is down. 200 30 k 500
11
DC or V SYNC
7V 0V 18
25
Note 1: The signal format for SYNC1-IN (pin 26) and SYNC2-IN (pin 24) NTSC (525I/60 Hz), PAL/SECAM (625I/50 Hz), NTSC Double Scan (525I/120 Hz), PAL/SECAM Double Scan (625I/100 Hz), 525P/60 Hz, 750P/60 Hz, 1125I/60 Hz, 1125P/30 Hz This IC doesn't have the sync-separation circuit for non-standard signals like weak strength signal, ghost signal and so on.
10
2006-02-27
TA1318AFG
Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal White 100 = 1 Vp-p 11 1 k 1 k 26 SYNC1-IN 1 k Input Y signal (Note 1) for sync separation circuit. Input via clamp capacitor. 26 or 1 k 4 VF
5
27
N.C.
Connect to GND.
11
VD output pin. Open collector output. VD1/VD2 input signals are output from this pin without synchronization. 28 VD1-OUT Polarity is switched by BUS write function. (Note) When HD PHASE will be changed, synchronized VD width will change. Use the start phase of VD. 18 28 200 Start phase
or
Start phase
Note 1: The signal format for SYNC1-IN (pin 26) and SYNC2-IN (pin 24) NTSC (525I/60 Hz), PAL/SECAM (625I/50 Hz), NTSC Double Scan (525I/120 Hz), PAL/SECAM Double Scan (625I/100 Hz), 525P/60 Hz, 750P/60 Hz, 1125I/60 Hz, 1125P/30 Hz This IC doesn't have the sync-separation circuit for non-standard signals like weak strength signal, ghost signal and so on.
11
2006-02-27
TA1318AFG
Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal
11 VD output pin. Open collector output. VD1/VD2 input signals are output from this pin without synchronization. 29 VD2-OUT Polarity is switched by BUS write function. (Note) When HD PHASE will be changed, synchronized VD width will change. Use the start phase of VD. 18 29 200 Start phase
or
Start phase
11
DAC3 output pin. 30 DAC3 Open collector output. In Test mode, outputs test pulse for shipping. 30 500
DC or test pulse for shipping
18
12
2006-02-27
TA1318AFG
Bus Control Map
Write Mode
Slave Address: D8/DA/DCH
Sub-Add 00 01 02 03 D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB Preset MSB 1000 1000 1000 1000 LSB 0000 0000 0000 0000
H-FREQUENCY DAC1 V-FREQUENCY
HD1/VD1-OUT SW DAC2 CLP-PHS HD PHASE
HD2/VD2-OUT SW DAC3 TEST
SEPA LEVEL HD1-INV HD2-INV
FREQ DET SW
INPUT SW VD1-INV VD2-INV
Read Mode
Slave Address: D9/DB/DDH
D7 MSB 0 1 POR HD-IN D6 D5 D4 D3 V FREQUENCY DET H FREQUENCY DET D2 D1 D0 LSB
Bus Control Functions
Write Mode (*: Preset)
* H-FREQUENCY (Horizontal oscillation frequency) Switches horizontal frequency. *(10): 33.75 kHz (00): 15.75 kHz (01): 31.5 kHz (11): 45 kHz Note: To prevent a horizontal mislock, set (10) 33.75 kHz mode just before (01) 31.5 kHz mode setting when the horizontal frequency mode is switched to (01) 31.5 kHz mode.(wait time: 1 ms or more) Additionally, in 31.5 kHz mode, set (10) 33.75 kHz mode at first and set (01) 31.5 kHz mode again, when 525 p/625 p signal is pulled-in again from no-input. HD1/VD1-OUT SW (HD1/VD1 output switch) Switches output from pin 16/28. When set to 00, 01, or 10, outputs HD/VD without synchronization. When set to 11, outputs HD/VD from the sync circuit. (Note) Synchronized VD width will change, when HD PHASE will be changed. *(00): HD1/VD1 (01): HD2/VD2 (10): HD3/VD3 (11): Synchronized HD/VD HD2/VD2-OUT SW (HD2/VD2 output switch) Switches output from pin 19/29. When set to 00, 01, or 10, outputs HD/VD without synchronization. When set to 11, outputs HD/VD from the sync circuit. (Note) Synchronized VD width will change, when HD PHASE will be changed. *(00): HD1/VD1 (01): HD2/VD2 (10): HD3/VD3 (11): Synchronized HD/VD SEPA LEVEL (Sync separation level switch) Switches sync separation level of pin 24/26. Set values are the levels from sync tip. Sync separation level is changed according to the ratio of H-SYNC width during 1H period. *(00): 10IRE (01): 15IRE (10): 20IRE (11): 25IRE (at 1125I/60) DAC1 (DAC1 control) Controls 2-bit DAC (pin 12). *(10): 5 V (00): 1 V (01): 3 V (11): 7 V DAC2 (DAC2 control) Controls 2-bit DAC (pin 25). *(00): 1 V (01): 3 V (10): 5 V (11): 7 V DAC3 (DAC3 control) Controls open collector 1-bit DAC (pin 30). *(0): OPEN (HIGH) (1): ON (LOW)
*
*
*
*
*
*
13
2006-02-27
TA1318AFG
* TEST (Test mode) Switches DAC1, 2, and 3 outputs. Also used to test IC for shipping. *(0): DAC outputs are used as DAC. (1): DAC1 outputs V. SYNC to the frequency counter. DAC2 outputs H. SYNC or C. SYNC to the frequency counter. DAC3 outputs IC test pulse for shipping. HD1-INV (HD1 output polarity switch) Switches HD1 output (pin 16) polarity. When set to 0, positive HD input is output as negative HD. When set to 0, output from the sync circuit is output as negative HD. *(0): Normal (1): Inverse HD2-INV (HD2 output polarity switch) Switches HD1 output (pin 19) polarity. When set to 0, positive HD input is output as negative HD. When set to 0, output from the sync circuit is output as negative HD. *(0): Normal (1): Inverse V-FREQUENCY (Vertical frequency switch (pull-in range)) Sets vertical frequency pull-in range, VD-STOP, or free-running frequency. Free-running frequency is controlled by H-FREQUENCY.
*
*
*
Pull-in Range *(000) (001) (010) (011) (100) (101) (110) (111) 48~1281 H 48~849 H FREE-RUN 48~637 H 48~613 H 48~363 H 48~307 H VP STOP
Format/H (V) Frequency 1125P/30 Hz (33.75 kHz) 750P/60 Hz (45 kHz) Free-running frequency is controlled by H-FREQUENCY. (00): 262 H (01): 525 H (10): 562 H (11): 750 H 1125I/60 Hz (33.75 kHz) 525P/60 Hz (31.5 kHz) PAL/SECAM/50 Hz (15.625 kHz) PAL/SECAM double scan/100 Hz (31.5 kHz) NTSC/60 Hz (15.734 kHz) NTSC double scan /120 Hz (31.5 kHz) VD output is HIGH
*
*
*
*
*
*
CLP PHS (Clamp pulse phase switch) Switches clamp pulse phase. If no signal input, 0.9 s pulse is output from the H-C/D circuit. *(0): 1 s (3.4%) delay following HD stop phase, 0.8 s (2.7%) pulse (1): 0.5 s (1.7%) delay following HD stop phase, 0.8 s (2.7%) pulse FREQ DET SW (Horizontal/vertical frequency counter switch) Switches input signal used for horizontal/vertical frequency counter. This switch is controlled independently from INPUT SW. The detection result is output as read BUS data. *(00): SYNC1 input (01): SYNC2 input (10)/(11): HD3/VD3 inputs INPUT SW (Input signal switch for synchronization) Switches input signal used for synchronization. *(00): SYNC1 input (01): SYNC2 input (10)/(11): HD3/VD3 inputs HD PHASE (HD phase adjustment) Adjusts phase of HD output from the sync circuit. The phase of the adjustment center value is the same as that of input H-SYNC or input HD. (Note) Synchronized VD width will change, when HD PHASE will be changed. -5% (H periodically) (000000) : *(100000) : 0% (111111) : 5% VD1-INV (VD1 output polarity switch) Switches VD1 output (pin 28) polarity. When set to 0, negative VD input is output as negative VD. When set to 0, output from the sync circuit is output as negative VD. *(0): Normal (1): Inverse VD2-INV (VD2 output polarity switch) Switches VD2 output (pin 29) polarity. When set to 0, negative VD input is output as negative VD. When set to 0, output from the sync circuit is output as negative VD. *(0): Normal (1): Inverse
14
2006-02-27
TA1318AFG
Read Mode
* POR (Power on reset) (0): Status read (at second data read and subsequent) (1): Power on (at first data read) HD-IN (Input signal self-check result) Detects HD or H-SYNC input signal selected by INPUT SW. (0): No signal input (1): Signal input V FREQ DET (Vertical frequency of SYNC or VD input selected by FREQ DET SW) (0000000)(0001100): No-VD (0001101) : Vicinity of 162 Hz (1111111) : Vicinity of 17 Hz How to calculate vertical frequency (X): Convert V-FREQ DET read data into decimal and define the resulting value as Y. Where H-FREQUENCY is 15.75 kHz/31.5 kHz, Z = 476.2 s Where H-FREQUENCY is 33.75 kHz/45 kHz, Z = 474.1 s Vertical frequency (X) = 1 / (Y x Z) [Hz] Error of Y is +1, -0. If vertical frequency is 162 Hz or more, the frequency cannot be accurately measured. Time constant used to separate V.SYNC from integrated C.SYNC is 9 s (error: 1 s). H FREQ DET (Horizontal frequency of SYNC or HD input selected by FREQ DET SW) (0000000): No signal input (1111111): 53 kHz or more How to calculate horizontal frequency (X): X, Y, and Z are defined same as for V FREQ. Horizontal frequency (X) = Y / (5 x Z) [kHz] Error of Y is +1, -0. If horizontal frequency is 53 kHz or more, the frequency cannot be accurately measured. When V-SYNC or VD is not input, horizontal frequency cannot be measured, resulting in data = (0000000). Note 1: The start trigger for frequency counting is the internal reset-pulse made from ACK of 2nd byte in BUS read mode. The counting period is between the first V-sync (VD) and the second V-sync (VD) after the trigger. The counted data will have +1 or -0 error according to the read timing. To assume stable data reading; 1. Set BUS reading interval more than 3 V. 2. Don't use the first data because it is unsettled. are recommended. Note 2: Ignore data (H FREQUENCY DET, V FREQUENCY DET) = (0000001, 0001101). This data is obtained when the pin voltage of SYNC-IN pin is higher than sync separation level and when any signal is not inputted into SYNC-IN pin.
*
*
*
Start trigger 1 Read Timing More than 3 V V-SYNC or VD
Data 1 and Start trigger 2
Data 2 and Start trigger 3
Counting period 1 (to Data 1)
Counting period 2 (to Data 2)
Decision algorithm (detection range, detection times and so on) should be determined under consideration of Note 1, Note 2 and the other factors such as signal strength, existence of ghost signal, H-AFC stability, I2C BUS data transmission and so on via prototype TV set evaluation.
15
2006-02-27
TA1318AFG
Data Transfer Format via I C BUS
Slave Address: D8/DA/DCH
A6 1 A5 1 A4 0 A3 1 A2 1 A1 0/1 A0 0/1 W/R 0/1
2
Start and Stop Condition
SDA
SCL S Start condition P Stop condition
Bit Transfer
SDA
SCL
SDA stable
Change of SDA allowed
Acknowledge
SDA by transmitter
Bit 9: High impedance
SDA by receiver Only bit 9: Low impedance
SCL from master S
1
8
9 Clock pulse for acknowledgment
16
2006-02-27
TA1318AFG
Data Transmit Format 1
S Slave address 7 bit 0A Sub address 8 bit A Transmit data 8 bit MSB P: Stop condition AP
MSB S: Start condition
MSB A: Acknowledge
Data Transmit Format 2
S Slave address 0A Sub address A Transmit data A A AP
Sub address
Transmit data n
Data Receive Format
S Slave address 7 bit
MSB
1A
Received data 1 8 bit
MSB
A
Received data 2
AP
At the moment of the first acknowledge, the master transmitter becomes a master receiver and the slave transmitter. This acknowledge is still generated by this slave. The Stop condition is generated by the master. (* important) The data read from THIS IC should always be completed in whole two words, not one word, otherwise the IICBUS may cause error.
Optional Data Transmit Format: Automatic Increment Mode
S Slave address 7 bit MSB 0A1 Sub address 7 bit A Transmit data 1 8 bit MSB
Transmit data 2 8 bit MSB
AP
MSB
In this transmission method, data is set on automatically incremented sub-address from the specified sub-address.
I2C BUS Conditions
Characteristics Low level input voltage High level input voltage Low level output voltage at 3 mA sink current Input current each I/O pin with an input voltage between 0.1 VDD and 0.9 VDD Capacitance for each I/O pin SCL clock frequency Hold time START condition Low period of SCL clock High period of SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Set-up time for STOP condition Bus free time between a STOP and START condition Symbol VIL VIH VOL1 Ii Ci fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF Min 0 3.0 0 -10 0 4.0 4.7 4.0 4.7 280 250 4.0 4.7 Typ. Max 1.5 Vcc 0.4 10 10 100 Unit V V V A pF kHz s s s s ns ns s s
17
2006-02-27
TA1318AFG
Absolute Maximum Ratings (Ta = 25C)
Characteristics Supply voltage Input pin voltage Input pin signal voltage Power dissipation Power dissipation reduction rate Operating temperature Storage temperature Symbol VCCmax Vin einmax PD (*1) 1/ja Topr Tstg Rating 12 GND - 0.3~VCC + 0.3 9 1136 9.1 Unit V V Vp-p mW mW/C
-20~65 -55~150
C C
Note 1: Refer to the figure below. Note 2: It is possible that this IC function faultily caused by leak problems according to a field intensity from CRT. Put this IC lay-out position to CRT be far more than 20 cm. If there is not enough distance, intercept it by a shield. Note 3: Pins 24 and 26 are susceptible to damage from surge voltages and should be handled with extreme care.
1136
Power consumption reduction ratio PD (mW)
773
0 0
25
65
150
Ambient temperature
Ta
(C)
Figure PD - Ta Curve
18
2006-02-27
TA1318AFG
Operating Condition
Characteristics Power supply voltage (VCC) HD1, HD2, HD3 Input level VD1, VD2, VD3 Input level Synchronization HD3 input width Frequency detection Pin 14 Synchronization VD3 input width Frequency detection Pin 13 SYNC1, SYNC2 Input level HD1, HD2, VD1, VD2-OUT Input current DAC3 Input current Address switching voltage Pin 26, 24, white 100% with negative sync Pin 16, 19, 28, 29 Pin 30 Pin 23 D8/D9H DC/DDH Pin 13 Pin 11 Pin 3, 1, 14 Pin 4, 2, 13 Pin 14 Description Min 8.5 2.0 2.0 0.02 0.45 s 1 s 1 0.9 Typ. 9.0 5.0 5.0 Max 9.5 9.0 9.0 0.20 0.25H 47H 400 1.1 1.5 mA 1.0 1.0 V 8.0 9.0 9.0 Vp-p H Unit V

1.0 0.9 0.5 0
s
Vp-p

0
Note: Pins 24 and 26 are susceptible to damage from surge voltages. Do not connect either of pins to an external input pin directly. When constructing a TV set, please consider to connect an external protection diode or a switch IC between any external input pin and pin 24 or 26.
19
2006-02-27
TA1318AFG
Electrical Characteristics (VCC = 9 V, Ta = 25C, unless otherwise specified) Current Dissipation
Pin Name VCC Symbol ICC Test Circuit Min 32 Typ. 38 Max 44 Unit mA
AC Characteristics Horizontal Block
Characteristics Sync1/2 input horizontal sync phase HD3 input horizontal sync phase Polarity distinction active range Symbol S1PH S2PH HD3PH HD-DUTY1 HD-DUTY2 VthS10 VthS11 VthS12 Sync1 input threshold amplitude Sync2 input threshold amplitude VthS13 VthS20 VthS21 VthS22 VthS23 HD3 input threshold amplitude (Synchronization block) HD1 input threshold voltage HD2 input threshold voltage HD3 input threshold voltage (SW block) VthHD3 VthHD1 VthHD2 VthHD3 Test Circuit Test Condition (Note HA01) (Note HA02) (Note HA03) 48 0.040 0.060 0.081 0.102 (Note HA04) 0.040 0.060 0.081 0.102 (Note HA05) 0.65 0.65 (Note HA06) 0.65 0.65 2.86 2.86 1.43 1.43 (Note HA07) 1.33 1.33 1.00 1.00 0.85 0.65 4.7 0.35 (Note HA08) 0.65 4.7 0 0.50 4.7 1.48 1.48 1.11 1.11 1.00 0.80 5.0 0.50 0.80 5.0 1.63 1.63 1.22 1.22 1.15 0.95 5.3 0.65 0.95 5.3 1 1.30 5.3 V V V 0.070 0.106 0.142 0.178 0.75 0.75 0.75 0.75 3.18 3.18 1.59 1.59 0.100 0.152 0.203 0.255 0.85 0.85 0.85 0.85 3.49 3.49 1.75 1.75 Vp-p Vp-p 53 0.070 0.106 0.142 0.178 58 0.100 0.152 0.203 0.255 Vp-p Min 0.6 0.6 0.6 61 Typ. 0.7 0.7 0.7 66 Max 0.8 0.8 0.8 71 % Unit

s s
HP0- HP0+ HP1-
HD output phase adjustment variable range

HP1+ HP2- HP2+ HP3- HP3+
CPS0 CPW0 CPV0 CPS1
s
s
Clamp pulse phase/width/level
CPW1 CPV1 CPS3 CPW3 CPV3

s
0.90 5.0
s
20
2006-02-27
TA1318AFG
Characteristics Delayed HD pulse width Symbol Wd-HD V13TH0 V13TL0 V13TH1 V13TL1 HD1 output voltage V13TH2 V13TL2 V13TH3 V13TL3 V15TH0 V15TL0 V15TH1 V15TL1 HD2 output voltage V15TH2 V15TL2 V15TH3 V15TL3 V13IH0 V13IL0 V13IH1 V13IL1 HD1 output voltage (polarity inverse) V13IH2 V13IL2 V13IH3 V13IL3 V15IH0 V15IL0 V15IH1 V15IL1 HD2 output voltage (polarity inverse) V15IH2 V15IL2 V15IH3 V15IL3 ID1 ID2 AFC phase detection current ID3 ID4 VCO oscillation start voltage VVCO TH00 HD output pulse width (free-run) TH01 TH10 TH11 Test Circuit Test Condition (Note HA09) Min 1.0 4.5 Typ. 1.2 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 385 385 650 650 4.2 1.8 1.8 1.8 1.8 Max 1.4 5.5 0.5 5.5 0.5 V 5.5 0.5 5.5 0.5 5.5 0.5 5.5 0.5 V 5.5 0.5 5.5 0.5 5.5 0.5 5.5 0.5 V 5.5 0.5 5.5 0.5 5.5 0.5 5.5 0.5 V 5.5 0.5 5.5 0.5 460 460 780 780 4.5 2.2 2.2 2.2 2.2 V Unit

s
4.5

4.5
4.5
4.5
4.5

4.5
4.5
4.5
4.5

4.5
4.5
4.5
4.5
4.5
4.5
310 310 (Note HB01) 520 520 (Note HB02) 3.9 1.4 1.4 (Note HB03) 1.4 1.4
A
s
21
2006-02-27
TA1318AFG
Characteristics Symbol F00 F01 Horizontal free-run frequency F10 F11 F50 BH00 Horizontal oscillation control sensitivity BH01 BH10 BH10 VDAC10 DAC1 output voltage VDAC11 VDAC12 VDAC13 VDAC20 DAC2 output voltage VDAC21 VDAC22 VDAC23 DAC3 output voltage VDAC30 VDAC31 Test Circuit Test Condition Min 15.59 31.19 (Note HB04) 33.41 44.55 15.47 2.4 4.8 (Note HB05) 4.8 7.1 0.5 6.0 8.9 1.0 3.0 5.0 7.0 1.0 3.0 5.0 7.0 0.5 8.8 7.2 10.7 1.5 3.3 V 4.7 6.5 0.5 5.3 7.5 1.5 3.3 V 4.7 6.5 5.3 7.5 0.7 V Typ. 15.75 31.5 33.75 45 15.625 3.0 6.0 Max 15.91 31.82 34.09 45.45 15.78 3.6 7.2 kHz/V kHz Unit

2.7

2.7
8.5
22
2006-02-27
TA1318AFG
Vertical Block
Characteristics VD1 input threshold voltage VD2 input threshold voltage VD3 input threshold voltage (SW block) VD3 input threshold voltage (synchronization block) Symbol VthVD1 VthVD2 VthVD3 VthVD3 V22TH0 V22TL0 V22TH1 V22TL1 VD1 output voltage V22TH2 V22TL2 V22TH3 V22TL3 V23TH0 V23TL0 V23TH1 V23TL1 VD2 output voltage V23TH2 V23TL2 V23TH3 V23TL3 V22IH0 V22IL0 V22IH1 V22IL1 VD1 output voltage (polarity inverse) V22IH2 V22IL2 V22IH3 V22IL3 V23IH0 V23IL0 V23IH1 V23IL1 VD2 output voltage (polarity inverse) V23IH2 V23IL2 V23IH3 V23IL3 VPW0 Vertical output pulse width VPW1 VPW2 VPW3 Test Circuit Test Condition Min 0.65 (Note VA01) 0.65 0.65 (Note VA02) 0.65 4.5 Typ. 0.75 0.75 0.75 0.75 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 5.0 0.1 286 143 133 100 Max 0.85 0.85 0.85 0.85 5.5 0.5 5.5 0.5 V 5.5 0.5 5.5 0.5 5.5 0.5 5.5 0.5 V 5.5 0.5 5.5 0.5 5.5 0.5 5.5 0.5 V 5.5 0.5 5.5 0.5 5.5 0.5 5.5 0.5 V 5.5 0.5 5.5 0.5 321 160 150 112 Vp-p Vp-p Unit

4.5
4.5
4.5
4.5

(Note VA03)
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
251 126 117 88
s
23
2006-02-27
TA1318AFG
Characteristics Symbol FV0 FV1 FV3 FV4 Vertical free-run frequency FV5 FV6 FV20 FV21 FV22 FV23 FVPL0 FVPL1 Vertical pull-in range FVPL2 FVPL3 15.75 kHz Sync input-VD output phase difference 31.50 kHz 33.75 kHz 45.00 kHz Test Circuit Test Condition Min 26.02 39.21 52.20 54.24 (Note VA04) 91.28 107.8 57.0 57.0 57.0 57.0 311 624 (Note VA05) 668 891 9.6 689 918 11.8 6.8 6.4 5.2 710 947 14.0 7.9 7.5 6.0 Typ. 26.35 39.75 52.98 55.06 92.98 109.9 60.0 60.0 60.0 60.0 321 643 Max 26.67 40.30 53.77 55.89 94.69 112.1 63.0 63.0 63.0 63.0 332 663 Hz Hz Unit

5.7 5.3 4.4
s
24
2006-02-27
TA1318AFG
Test Conditions and Measuring Method
Note Item S06 HA01 Sync1/2 input horizontal sync phase c SW Mode S18 b S19 a b S21 b a (1) (2) (3) (4) (5) (6) (7) (8) (9) Set sub-address (02) 60. SW19-a and SW21-b. Input Signal a (horizontal 33.75 kHz ) to pin 21 (SYNC1-IN). Set sub-address (02) 61. Measure the phase difference S1PH between pin 21 and pin 6 (AFC filter) wave form. SW19-b and SW21-a. Input Signal a (33.75 kHz ) to pin 19 (SYNC2-IN). Set sub-address (02) 01. Measure the phase difference S2PH between pin 19 and pin 6 (AFC filter) wave form. Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 3C, unless otherwise specified)
29.63 s 0.593 s Signal a 0.285 V S1PHS2PH Pin 6 wave form
25
2006-02-27
TA1318AFG
Note Item S06 HA02 HD3 input horizontal sync phase c SW Mode S18 b S19 S21 (1) (2) (3) Set sub-address (00) 40 and (02) 82. Input signal b (horizontal 31.5 kHz ) to pin 11 (HD3-IN). Measure the phase difference HD3PH between pin 11 and pin 6 (AFC filter) wave form. 31.75 s 2.35 s Signal b 1.5 V Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 3C, unless otherwise specified)
HD3PH Pin 6 wave form
HA03
Polarity distinction active range
c
b
(1) (2) (3) (4)
Set sub-address (00) 70 and (02) 82. Input signal b ((horizontal 31.5 kHz ) to pin 11 (HD3-IN). Decreasing the duty of signal b to 0% (get negative period shorter), measure the duty of Signal b (HD-DUTY1) when the phase between pin 11 and pin 13 (HD1-OUT) change. Increasing the duty of Signal b to 100% (get negative period longer), measure the duty of Signal b (HD-DUTY2) when the phase between pin 11 and pin 13 (HD1OUT) change.
31.75 s 2.35 s Signal b 1.5 V
B
A * duty = A/(A + B) x 100 (%)
26
2006-02-27
TA1318AFG
Note Item S06 HA04 Sync1 input threshold amplitude Sync2 input threshold amplitude c SW Mode S18 b S19 a b S21 b a (1) (2) (3) (4) (5) (6) (7) Set sub-address (00) 0B and (02) 60. Input Signal a (33.75 kHz) to pin 21 (SYNC1-IN) Measure the sync. tip DC voltage of signal a on pin 21 (SYNC1-IN). (Vsync11) Supply external voltage via 100 k to pin 21 and increase the voltage. Measure the sync. tip DC voltage (Vsync12) when HD-OUT desynchronizes with signal a calculate VthS10. VthS10 = Vsync12 - Vsync11 Set sub-address (00) B1, B2 and B3 and calculate VthS11, VthS12 and VthS13 as well. Calculate VthS20, VthS21, VthS22 and VthS23 against pin 19 (SYNC2-IN) in the same way as 4 to 6. Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 3C, unless otherwise specified)
29.63 s 0.593 s Signal a 0.285 V
HA05
HD3 input threshold amplitude (synchronization block)
c
b
(1) (2) (3)
Set sub-address (00) 70 and (02) 62. Input Signal b (31.5 kHz) to pin 11 (HD3-IN). Increasing the voltage of Signal b from 0 V, measure the voltage of Signal b VthHD3 when HD1-OUT lock.
31.75 s 2.35 s Signal b VthHD1
27
2006-02-27
TA1318AFG
Note Item S06 HA06 HD1 input threshold voltage HD2 input threshold voltage HD3 input threshold voltage (SW block) c SW Mode S18 b S19 S21 (1) (2) (3) (4) Set sub-address (00) 40. Input Signal b (31.5 kHz) to pin 3 (HD1-IN). Increasing the voltage of Signal b from 0 V, measure the voltage of Signal b VthHD1 when HD1-OUT lock. Measure the voltage of pin 1 VthHD2. Measure the voltage of pin 11 VthHD3 as well. Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 3C, unless otherwise specified)
31.75 s 2.35 s Signal b VthHD1
28
2006-02-27
TA1318AFG
Note Item S06 HA07 HD output phase adjustment variable range c SW Mode S18 b S19 S21 (1) (2) (3) (4) (5) (6) (7) (8) Set sub-address (00) 30. Input Signal b (horizontal period T = 63.5 s) to pin 11 (HD3-IN). Set sub-address (02) 02. Change form 00 to 7C sub-address (03), then measure the phase change quantity (HP0-) of pin 13 (HD1-OUT) wave form. Change form 80 to FC sub-address (03), then measure the phase change quantity (HP0+) of pin 13 (HD1-OUT) wave form. When horizontal period of Signal b is T = 31.75 s measure HP1- and HP1+ as well. When horizontal period of Signal b is T = 29.63 s measure HP2- and HP2+ as well. When horizontal period of Signal b is T = 22.22 s measure HP3- and HP3+ as well. T s 2.35 s Signal b 1.5 V Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 3C, unless otherwise specified)
Pin 15 wave form data (00) HP*- Pin 15 wave form data (7C) (80) HP*+ Pin 15 wave form data (FC)
29
2006-02-27
TA1318AFG
Note Item S06 HA08 Clamp pulse phase/width/level c SW Mode S18 b S19 S21 (1) (2) (3) (4) (5) (6) (7) (8) Set sub-address (00) B0. Input Signal a (horizontal 33.75 kHz) to pin 11 (HD3-IN). Set sub-address (02) 02. Measure the clamp pulse phase (CPS0), width (CPW0), output level (CPV0) of pin 12 (CLP-OUT) against Signal a. Set sub-address (02) 12. Measure the clamp pulse phase (CPS1), width (CPW1), output level (CPV1) of pin 12 (SCP-OUT) against Signal a. Input no-signal to pin 11. Measure the clamp pulse phase (CPS2), width (CPW2), output level (CPV2) of pin 12 (SCP-OUT) against pin 13 (HD-OUT). 29.63 s 2.35 s Signal a 1.5 V CPS0CPS1 Pin 12 wave form CPV0CPV1 CPW0CPW1 Pin 13 wave form CPS3 Pin 12 wave form CPV3 CPW3 Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 3C, unless otherwise specified)
30
2006-02-27
TA1318AFG
Note Item S06 HA09 Delayed HD pulse width c SW Mode S18 b S19 S21 (1) (2) (3) (4) Set sub-address (00) 70. Input Signal b (horizontal 31.5 kHz) to pin 11 (HD3-IN). Set sub-address (02) 62. Measure the pulse width (WdHD) of pin 6 (AFC filter) wave form. Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 3C, unless otherwise specified)
31.75 s 2.35 s Signal b 1.5 V
Wd-HD Pin 6 wave form
31
2006-02-27
TA1318AFG
Note Item S06 HB01 AFC phase detection current OPEN SW Mode S18 b S19 a S21 b (1) (2) (3) (4) (5) (6) (7) BUS control data preset. Horizontal oscillation frequency is 15.75 kHz (00). SW6 open. Measure the Voltage of pin 6 V6 (no external supply). Connect external supply with pin 6, and supply the voltage (V6). Input signal (below figure) to pin 21 (SYNC1-IN). When INPUT SW is SYNC1-IN , measure V1 and V2 of pin 6 wave form. Supply V6 - 0.1 V and V6 + 0.1 V to pin 6, then measure V3 and V4. Calculate by following equations. ID1 [A] = (V1 [V] / 1 [k]) x 1000 ID2 [A] = (V2 [V] / 1 [k]) x 1000 ID3 [A] = (V3 [V] / 1 [k]) x 1000 ID4 [A] = (V4 [V] / 1 [k]) x 1000 Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 3C, unless otherwise specified)
63.5 s Pin 21 wave form 0.25 V
V1, V3 Pin 6 wave form V2, V4
HB02
VCO oscillation start voltage

(1)
Increasing the voltage of pin 8 VCC form 2.5V, measure the voltage VVCO when pin 7 appear oscillation wave form.
32
2006-02-27
TA1318AFG
Note Item S06 HB03 HD output pulse width (free-run) c SW Mode S18 b S19 S21 (1) (2) (3) BUS control data preset. When horizontal oscillation frequency is 15.75 kHz (00), measure the output pulse width TH00 of pin 13 (HD1-OUT) wave form. When horizontal oscillation frequency is 31.5 kHz (01), 33.75 kHz (10), 45 kHz (11), measure the output pulse width TH01, TH02, TH03 as well. Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 3C, unless otherwise specified)
Pin 13 (HD1OUT) wave form TH
HB04
Horizontal free-run frequency
OPEN
b
(1) (2) (3) (4)
BUS control data preset. SW6 open. When horizontal oscillation frequency is 15.75 kHz (00), measure the oscillation frequency F00 of pin 13 (HD1-OUT) wave form. When horizontal oscillation frequency is 31.5 kHz (01), 33.75 kHz (10), 45 kHz (11), measure the oscillation frequency F01, F10, F11 as well. When horizontal oscillation frequency is 15.75 kHz (00) and vertical free-run frequency is (101), measure the oscillation frequency F50 of pin 15 wave form. BUS control data preset. SW6 open. Connect external voltage with pin 6 . Horizontal oscillation frequency is 15.75 kHz (00). Supply V6 (about 6.3 V) + 0.05 V or V6 - 0.05 V to pin 6, then measure the frequency FA, FB of pin 13 (HD1-OUT) wave form. Calculate frequency changing ratio (BH00). BH00 = (FB - FA)/0.1 When horizontal oscillation frequency is 31.5 kHz (01), 33.75 kHz (10), 45 kHz (11), calculate BH01, BH10, BH11 as wall.
HB05
Horizontal oscillation control sensitivity OPEN
b
(1) (2) (3)
(4)
33
2006-02-27
TA1318AFG
Note Item S06 VA01 VD1 input threshold voltage VD2 input threshold voltage VD3 input threshold voltage (SW block) c SW Mode S18 b S19 S21 (1) (2) (3) (4) (5) Set sub-address (00) 80. Input Signal a (vertical 60 Hz) to pin 4 (VD1-IN). Set sub-address (02) 00. Increasing the voltage of Signal a from 0 V. measure the voltage of Signal b VthVD1 when VD1-OUT lock. Measure VthVD2 and VthVD3 against pin 2 and pin 10 as wall. Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 3C, unless otherwise specified)
16.67 ms 0.12 ms Signal a VthVD1
VA02
VD3 input threshold voltage (synchronization block)
c
b
(1) (2) (3) (4)
Set sub-address (00) 70. Input Signal b (vertical 60 Hz) to pin 10 (VD3-IN). Set sub-address (02) 03. Increasing the voltage of Signal b from 0 V, measure the voltage of Signal a VthVD3 when VD1-OUT lock.
16.67 ms 0.12 ms Signal a
34
2006-02-27
TA1318AFG
Note Item S06 VA03 Vertical output pulse width c SW Mode S18 b S19 S21 (1) (2) (3) (4) Input Signal a (horizontal 33.75 kHz) to pin 11 (HD3-IN). Set sub-address (02) 02. When sub-addrss (00) is B0, measure the pulse width VPW2 of pin 22 (VD1-OUT) wave form. When sub-addrss (00) is 30, 70, F0, measure the pulse width VPW0, VPW1, VPW3 of pin 22 (VD1-OUT) wave form as well. Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 3C, unless otherwise specified)
29.63 s 0.593 s Signal a V period Pin 22 wave form
VPW*
35
2006-02-27
TA1318AFG
Note Item S06 VA04 Vertical free-run frequency c SW Mode S18 b S19 S21 (1) (2) (3) (4) (5) (6) Input Signal a (horizontal 33.75 kHz) to pin 11 (HD3-IN). Set sub-address (00) B0. When sub-address (02) is 02, 22, 62, 82, A2 or C2, measure the frequency FV0, FV1, FV3, FV4, FV5 or FV6 of pin 22 (VD1-OUT) wave form. Input no-signal to pin 3 (HD1-IN). Set sub-address (02) 42. When sub-address (00) is 30, 70, B0 or F0, measure the frequency FV20, FV21, FV22 or FV23 of pin 22 (VD1-OUT) wave form. Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 3C, unless otherwise specified)
29.63 s 0.593 s Signal a 0.285 V V period Pin 22 wave form
VPW*
36
2006-02-27
TA1318AFG
Note Item S06 VA05 Vertical pull-in range c SW Mode S18 b S19 S21 (1) (2) (3) (4) (5) (6) (7) (8) (9) Input Signal a (horizontal period T = 63.5 s) to pin 11 (HD3-IN). Set sub-address (02) 02. Set sub-address (00) 30. Input Signal C (vertical period initial T = 1ms) to pin 10 (VD3-IN). Increasing vertical period of Signal C, measure the frequency FVPL0 when pin 22 (VD1-OUT) wave form synchronize with Signal C. Input Signal a (horizontal period T = 31.75 s) to pin 11 (HD3-IN). Set sub-address (00) 70. Measure FVPL1 as well. Input Signal a (horizontal period T = 29.63 s) to pin 11 (HD3-IN). Set sub-address (00) B0. Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 3C, unless otherwise specified)
(10) Measure FVPL2 as well. (11) Input Signal a (horizontal period T = 22.22 s) to pin 11 (HD3-IN). (12) Set sub-address (00) F0. (13) Measure FVPL3 as well.
horizontal period Ts 0.593 s Signal a 1.5 V V period (initial T = 1 ms) 0.25 ms Signal c 1.5 V
measuring period Pin 22 wave form
37
2006-02-27
9V 100 F 0.01 F 9V REG. 5V 100 F 100 30 1 HD2-IN 10 k #24 DAC3 #1 0.01 F Pin 1 100 29 2 VD2-IN #23 VD2-OUT #2 68 k SW6 a 7 bc #6 2.2 F 7.5 k AFC Filter Pin 6 1 k 6 NC 10 k Pin 2 100 3 HD1-IN VD1-OUT #3 28 Pin 3 100 4 VD1-IN #4 Pin 4 5 Analog GND NC SYNC1-IN DAC1 SYNC2-IN #22 27 a SYNC1 1 F 26 #21 25 #20 24 #19 100 a b SW19 1 F b SW21 5.1 k 5.1 k
Test Circuit
ab Pin 20 SW18 SYNC2
TA1318AFG
38
M 0.01 F
23
8 9
NC
Address SW
c
#18
CSBLA503 KECZF30 360 Pin 7 0.01 F 12 100 100 100 100 HVCO #7 10 11
22 SCL #17 21 SDA NC #16 20 NC VCC
0.01 F
100
SCL 100 SDA
100 F Pin 9 Pin 10 Pin 11 Pin 12
19
DAC2 #9 13 #10 14 #11 15 #12
HD2-OUT
5.1 k #15 18 VD3-IN DIGITAL GND
17 NC HD3-IN 16
CP-OUT
HD1-OUT
5.1 k #13
100 F 0.01 F 1 k 5.1 k 10 F 3.9 k 1 k 5.1 k 10 F 3.9 k
M Mylar capacitor
TPS1-in
TA1318AFG
TPS2-in 75
2006-02-27
75
TA1318AFG
Application Circuit 1 (Typical values)
9V 0.01 F 100 F DAC3 15 k 10 k VD2OUT 10 k VD1OUT SYNC1SYNC2DAC1 IN IN SCL 100 SDA 10 k 100 HD2OUT 10 k 19 HD2-OUT 18 DIGITAL GND 17 NC 16 HD1-OUT 15
M Mylar capacitor
HD1OUT
1 F
30 DAC3
29 VD2-OUT
28 VD1-OUT
27 NC
26 SYNC1-IN
25 DAC1
1 F 24 SYNC2-IN
23 Address SW
22 SCL
21 SDA
20 NC
TA1318AFG
Analog GND
AFC Filter
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0.01 F 360 HD2-IN VD2-IN HD1-IN VD1-IN
M 0.01 F
100 F DAC2 VD3-IN HD3-IN CP-OUT
2.2 F
7.5 k
CSBLA503KECZF30
CP-OUT
HD2-IN
HD1-IN
HD3-IN
VD2-IN
VD1-IN
VD3-IN
HVCO
DAC2
NC
NC
NC
VCC
39
2006-02-27
TA1318AFG
Application Circuit 2 (How to measure H/V frequency)
To measure H/V frequency of signal 2 (fH2: unknown) correctly, use two separated input terminals as the following figure. One is for frequency measuring (SYNC2-in) and the other is for the AFC (SYNC1-IN). And measure H/V frequency of signal 2 (fH2: unknown) on condition that AFC is stable (AFC locks in signal 1 (fH1: known).) or that AFC is free-run when SYNC1-IN is no-signal.
Signal 1 (fH1: known) Signal 2 (fH2: unknown) SYNC1-IN for H-AFC
Signal 1
AFC BUS READ
Internal pulse (A)
H/V FREQ COUNTER
Signal 2 SYNC2-IN for H/V freq. counter TA1318AFG
This IC's H/V frequency counting is done by internal pulse (A) which is made in AFC circuit. So, if AFC circuit doesn't lock in the regular frequency, the frequency of pulse (A) will not be correct and the H/V frequency data will not be showed correct data. Decision algorithm of H/V frequency detection (detection range, detection times and so on) should be determined under consideration the factors such as signal strength, existence of ghost signal, H-AFC stability, I2C BUS data transmission and so on via prototype TV set evaluation.
40
2006-02-27
TA1318AFG
Package Dimensions
Weight: 0.63 g (typ.)
41
2006-02-27
TA1318AFG
About solderability, following conditions were confirmed * Solderability (1) Use of Sn-37Pb solder Bath * solder bath temperature = 230C * dipping time = 5 seconds * the number of times = once * use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder Bath * solder bath temperature = 245C * dipping time = 5 seconds * the number of times = once * use of R-type flux
RESTRICTIONS ON PRODUCT USE
* The information contained herein is subject to change without notice. 021023_D
060116EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C * The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E
42
2006-02-27

▲Up To Search▲

Price & Availability of TA1318AFG

	To Download TA1318AFG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .